1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns a method of planarizing the surface of a wafer using chemical mechanical polishing.
2. Description of the Related Art
Integrated circuits are typically comprised of a plurality of semiconductor devices formed in or on a semiconductor substrate. In current applications, integrated circuits can consist of literally thousands or millions of individual semiconductor devices formed in or on the substrate. Typically, large number of integrated circuits are formed on a single wafer by selectively exposing regions of the wafer so as to allow for deposition or implantation of impurities into the semiconductor wafer to thereby alter the characteristics of the semiconductor wafer to produce the desired different semiconductor devices. The semiconductor devices can be formed in the exposed regions of the wafer using well-known masking techniques in conjunction with well-known diffusion, implantation or deposition techniques.
Over the past several decades, the scale of integration of integrated circuits has increased. More particularly, semiconductor device fabrication techniques have been developed which allow for a higher density of semiconductor devices to be formed in the integrated circuits. As the scale of integration has increased and as the size of the individual semiconductor devices has decreased, it has become more important that integrated circuit designers and fabricators consider the structural integrity of the deposited devices and of the integrated circuit as a whole.
Repeated deposition of materials into the exposed regions of the wafer can result in the integrated circuit having a non-planar upper surface. As the upper surface of the integrated surface becomes less planar, the ability to form additional semiconductor devices on the integrated circuits becomes more difficult. Moreover, the existence of protrusions in the topography of the integrated circuit affects the structural integrity of the integrated circuit and can result in short circuits or failures. Consequently, integrated circuit designers and fabricators have increasingly used planarization techniques to planarize the upper surface of the integrated circuits.
One particular planarization technique is known as chemical mechanical polishing or planarization (CMP). CMP is a technique whereby the upper surface of a wafer is globally planarized by simultaneously abrasively polishing and etching the upper surface of the wafer. Basically, the wafer is positioned adjacent a pad that is rotated with respect to the wafer and the pad also contains a slurry which typically is comprised of an etchant liquid and an abrasive encapsulated within a suspension material. The rotating pad is then applied to the wafer so that protrusions in the surface topography of the integrated circuits on the wafer can be removed by a combination of abrasive polishing and etching.
One particular application where CMP has found great use is in removing protrusion in the surface topography extending above intermediate dielectric layers of an integrated circuit. Oftentimes, dielectric layers, such as BPSG Oxide (Boro-Phospho-Silicate Glass) is formed on the upper surface of a wafer so as to provide isolation or a dielectric between conductive layers and semiconductor devices formed in the wafer. After formation of the intermediate dielectric layer, cavities, such as trenches or vias, are often formed in the intermediate dielectric layer so that conductors can be deposited within the trenches or vias to allow for selective interconnection to the semiconductor devices within the semiconductor substrate or to circuit nodes positioned under the dielectric layer.
Typically, the conductive layers are formed by depositing conductive material such as Polysilicon, Tungsten, or Aluminum, on top of the intermediate dielectric layer using well-known deposition techniques, such as vacuum chamber deposition, spluttering and the like. While the deposition techniques will result in conductive material being deposited within the trenches and vias formed in the intermediate dielectric layer, a substantial portion of the conductive material will extend upward from the intermediate dielectric layer thereby resulting in less planarization of the upper surface of the integrated circuit.
To address this problem, CMP is often used to remove the excess portion of the conductive material that is positioned on top of the intermediate dielectric layer as a result of the deposition techniques. While CMP is well adapted for removing the excess conductive material, it is often difficult to control the rate of removal of the conductive material which can result in portions of the intermediate dielectric layer being inadvertently removed during the CMP process.
Hence, there is often a difficulty associated with thinning of the intermediate dielectric layer during the planarization and removal of excess conductive material step. As device integration on integrated circuits has increased, the tolerances of the required thicknesses for intermediate dielectric layers have become smaller. Consequently, this thinning of the dielectric layers during chemical mechanical planarization has become of greater concern in integrated circuit fabrication.
Hence, there is a need for a process whereby planarization of intermediate dielectric layers can be achieved which reduces inadvertent thinning of the dielectric layer during the planarization process. To this end, there is a need for a planarization technique, such as CMP, which is capable of planarizing a dielectric or Oxide layer to remove excess conductive material, but does not result in significant thinning of the underlying region or layer.